The invention relates to a semiconductor structure having buried track conductors and to a method for generating an electrical contact with buried track conductors.
According to the prior art, memory cell arrangements, for example flash memories, are produced as large matrix-like memory arrays comprising transistors. A certain arrangement of track conductors is required both for storage and to read out the memory cells. To optimize the space required, some of the track conductors are diffused into a semiconductor substrate as buried bit lines. However, diffused-in bit lines have the problem that the electrical resistances of the diffused-in bit lines are higher than the electrical resistances of track conductors in metallization levels.
The RC time constant which results from the level of the resistances of the diffused-in bit lines consequently limits the signal propagation time. The term signal propagation time is to be understood as meaning the time required to write to memory cells or to read them out. According to the prior art, to reduce the signal propagation time in each case one metallic track conductor is used in parallel to the diffused-in bit lines. These metallic track conductors are electrically connected to the diffused-in bit lines at regular intervals by means of contacts, known as stitch contacts. This allows the resistance of the diffused-in bit lines and therefore the signal propagation time to be reduced. For clarification, FIG. 1 and FIG. 2 show a semiconductor structure which represents a memory cell arrangement of this type.
FIG. 1 shows a top view of a semiconductor structure 100 in accordance with the prior art.
In a semiconductor substrate 101, a group of first track conductors 103 is integrated at a substrate surface 102. The first track conductors 103 are arranged parallel and next to one another and end substantially flush with the substrate surface 102. The first track conductors 103 are usually produced by means of diffusion of electrically conductive ions into the semiconductor substrate 101. The first track conductors 103 may, for example, be provided as buried bit lines.
Furthermore, on the substrate surface 102 of the semiconductor substrate 101 there is a group of second track conductors 104, which are arranged parallel and next to one another on the substrate surface 102, electrically insulated with respect to the first track conductors 103. Together with the first track conductors 103, the second track conductors 104 form a regular grid. The second track conductors 104 are usually produced by means of conventional methods for producing metallization levels.
In each case two adjacent first track conductors 103 and one second track conductor 104 which lies above them form a transistor. The two first track conductors 103 act as the two transistor electrodes known as source and drain in the transistor region, for which reason the first track conductors 103 are referred to as bit lines. In the transistor region, the second track conductor 104 acts as the transistor electrode known as gate, for which reason the second track conductors 104 are referred to as word lines.
On the substrate surface 102, in each transistor region an oxide-nitride-oxide layer sequence (not shown) comprising silicon dioxide (SiO2) and silicon nitride (Si3N4) is located between the first track conductors 103 and below each second track conductor 104, it being possible for up to two bits to be stored in the silicon nitride layer.
To reduce the electrical resistance, the first track conductors 103 are connected to metallic bit lines 106 by means of self-aligning contacts 105. These metallic bit lines 106 run in parallel over the first track conductors 103, bridge the second track conductors 104 and are electrically insulated with respect to the second track conductors 104. Contact is made between the first track conductors 103 and the metallic bit lines 106 in the direction of the metallic bit lines 106 by means of the self-aligning contacts 105 after in each case four second track conductors 104.
FIG. 2 shows a part of a cross section through the semiconductor structure 100 shown in FIG. 1, on section line A—A.
A first insulating layer 201 is located above the substrate surface 102 and therefore above the first track conductors 103, which are integrated in the semiconductor substrate 101. The first insulating layer 201 is intended to provide electrical insulation between the second track conductors 104 and the first track conductors 103. Furthermore, the second track conductors 104 are encapsulated by a second insulating layer 202, and a third insulating layer 203 fills up empty regions between the second track conductors 104, in order to ensure that the second track conductors 104 are electrically insulated with respect to the self-aligning contacts 105 and with respect to the metallic bit lines 106.
The following process sequence is usually employed to produce the self-aligning contacts 105: after the first insulating layer 201 and the second track conductors 104 have been produced, the second track conductors 104 are encapsulated by a second insulating layer 202. For this purpose, first of all an insulating material is deposited over the surface of the second track conductors 104. Then, an etching mask is applied above the second track conductors 104 and the insulating material at exposed locations which are not covered by the etching mask are removed all the way to the substrate surface 102. Then, the etching mask is removed again.
Then, the third insulating layer 203 is produced in the exposed openings between the second track conductors 104. In this case, the material used for the third insulating layer 203 is usually an insulating material which can be etched selectively with respect to the insulating material of the second insulating layer 202. By way of example, silicon nitride (Si3N4) can be used for the second insulating layer 202 and silicon dioxide (SiO2) for the third insulating layer 203.
To complete production of the self-aligning contacts 105, the third insulating layer 203 is now removed at certain places, and in this way the first track conductors 103 are locally uncovered again. These certain places are then filled with an electrically conductive material, for example tungsten, until the second insulating layer 202, the remaining third insulating layer 203 and the certain places which have been filled with electrically conductive material have a common surface 204 which is parallel to the substrate surface 102. The certain places which have been filled with electrically conductive material now act as self-aligning contacts 105.
In the end, the metallic bit lines 106 are located on the common surface 204 and are required for coupling of electrical signals into the semiconductor structure 100. Furthermore, the metallic bit lines 106 create the possibility of making contact with the integrated first track conductors 103 by means of a plurality of self-aligning contacts 105.
As has already been mentioned above, therefore, to reduce the signal propagation time, in accordance with the prior art in each case one metallic bit line is used in parallel with the diffused-in bit lines. The metallic bit lines are electrically connected to the diffused-in bit lines by means of the self-aligning contacts at intervals of four word lines. The contacts only align themselves perpendicular to the second track conductors.
However, the above-described method for producing the self-aligning contacts does not allow alignment parallel to the second track conductors. Therefore, there is a risk of a contact being produced offset parallel to the second track conductors. An offset contact of this type can lead to electrostatic effects on the semiconductor substrate, which can cause a short circuit between adjacent diffused-in bit lines. A short circuit of this type inevitably leads to failure of the immediately adjacent transistors. It is possible that all the transistors in the relevant bit lines may even be affected by this disturbance. Therefore, when the etching mask is being produced during the production process for each individual contact, the etching mask has to be positioned very accurately, which involves a high level of outlay.
The invention is therefore based on the problem of providing a semiconductor structure and a method for generating an electrical contact, in which the signal propagation times in the semiconductor structure are reduced further and more reliable contact is ensured.
The problem is solved by a semiconductor structure and a method for generating an electrical contact which have the features described in the independent patent claims.